1. Field of the Invention
This invention relates to clock monitoring circuits and, more particularly, to a circuit and method for monitoring the status of a first clock signal relative to a second clock signal. In one embodiment, the status indicates whether the frequency of the first clock signal is faster, slower or substantially equivalent to the frequency of the second clock signal.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many electronic systems, such as microprocessors and other integrated circuits, require stable clock signals to perform their internal operations. In very early integrated circuit (IC) microprocessor designs, the clock signals were provided by circuits external to the microprocessor, typically in the form of an off-chip integrated circuit dedicated to that purpose. In more recent designs, the clock signal generating circuits were integrated onto the same chip as the microprocessor or other device. Regardless of whether they are “on-chip” or “off-chip,” clock signal generating circuits usually rely upon an externally-located crystal oscillator to provide the reference frequency upon which the generated clock signal is based.
There are numerous ways in which a stable clock signal may be generated from an external reference clock signal. For example, frequency synthesizer circuits, such as a phase-locked loops (PLL) and delay-locked loops (DLL), are commonly used for generating relatively stable clock signals from a reference clock signal provided, e.g., by a crystal oscillator. In an ideal situation, frequency synthesis would result in one or more clocking signals, which are in phase and/or frequency alignment with the reference clock signal.
A PLL, for example, is a closed-loop device that utilizes a voltage-controlled oscillator (VCO) for obtaining accurate phase and frequency alignment between two signals, typically referred to as feedback and reference clock signals. Conventional PLLs generally include four main components: a phase frequency detector (PFD), a charge (or voltage) pump, a filter and a voltage controlled oscillator (VCO). The PFD monitors the phase/frequency difference between an externally-provided reference signal and a feedback signal generated by the VCO, and as a result, generates compensating “up” and “down” control signals when the feedback signal lags or leads the reference frequency or phase. The up/down control signals are passed through the charge pump and filter to produce a control voltage for controlling the VCO. The up/down control voltages drive the VCO (by increasing/decreasing the oscillation frequency therein) to maintain a predetermined phase relationship between the reference and feedback signals. Though similar, a DLL generally differs from a PLL in that it uses a delay line, instead of a VCO, for obtaining accurate phase and frequency alignment between the feedback and reference signals.
However, a problem occurs when the reference clock signal supplied to a PLL or DLL becomes unstable. For example, when the frequency of the reference clock signal drifts, or changes radically to a different rate, the output signal generated by the VCO (or delay line) follows suit by attempting to achieve phase lock with the new, albeit incorrect, frequency of the reference clock signal. This may cause data to be clocked at the wrong points, resulting in erroneous communication between integrated circuit components.
Many prior art systems have ways of detecting and reporting a momentary loss of phase lock caused by a relatively unstable or lost reference clock signal. For example, clock monitoring circuits are currently used for detecting the loss of a reference clock signal, and for producing or selecting an alternate clock signal to replace the lost signal. However, most prior art circuits cannot detect a loss of phase lock caused, e.g., by jitter or other sources of noise within the PLL or DLL. In other words, conventional clock monitoring circuits fail to identify the direction in which the feedback clock is pulling away from the reference clock when the PLL/DLL is “unlocked” and, therefore, cannot determine whether the feedback clock frequency is faster or slower than the reference clock frequency. The direction in which the PLL/DLL is pulling out of “lock” represents valuable information, which could be used for diagnosing or even correcting the state of the clock.
For at least these reasons, a need remains for an improved circuit and method for monitoring and reporting the status of a first clock signal (e.g., a feedback clock signal) relative to a second clock signal (e.g., a reference clock signal). The reported status preferably indicates whether the frequency of the first clock signal is faster, slower or substantially equivalent to (i.e., in phase/frequency lock with) the frequency of the second clock signal.